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Analog to Digital Converter (ADC)

Number of Channels4
Number of Bits16
Range Modes±10, ±5, ±2.5, ±1.25Volts
Quantization Step Size312.5 (Range=±10V)
156.25 (Range=±5V)
78 (Range=±2.5V)
39 (Range=±1.25V)
Maximum Sample Rate11MS/s
Input Impedance>100kΩ
Latency (Measurement to Data Ready)800ns
Input Filter Bandwidth (-3 dB)400kHz
Input Filter Delay (frequencies <100kHz)2550ns

Typical Noise of ADC3

ModeNoise (RMS)SNR4Effective # of bits5
±10V150µV93.5 dB15.2
±5V100µV91.0 dB14.8
±2.5V40µV92.9 dB15.1
±1.25V35µV88.0 dB14.3

Digital to Analog Converter (DAC)

Number of Channels4
Number of Bits16
Range Modes±10Volts
Quantization Step Size312.5µV
Maximum Sample Rate11MS/s
Output Impedance50Ω
Update Latency61.0µs
Output Filter Bandwidth (-3 dB)175kHz
Output Filter Delay (frequencies <100kHz)21.2µs

Timing Resolution

ParameterValue (Typical)Units
Interrupt Timing Jitter7100ns
Interrupt Latency (Best-case)7110ns
Interrupt Latency (Worst-case)7210ns

GPIO & Trigger Lines

Minimum Voltage0V
Maximum Voltage3.3V
Output Impedance200Ω
Logic Levels (Input & Output)3.3V CMOS

  1. Mega Samples Per Second (MS/s) across all channels. Sum of sample rate of all channels must not be greater than 1 MS/s.
  2. See Analog Response Time App Note for details on time delay caused by analog filters.
  3. For Quarto hardware 5.1 and higher. For noise specs on earlier Quarto units, please contact qNimble.
  4. SNR defined as the ratio of power of a full-scale sine wave to the power of the noise.
  5. Effective Number of Bits defined as the SNR1.766.02\frac{SNR - 1.76}{6.02}. See Wikipedia definition for more details.
  6. Time from executing writeDAC function to analog output starts changing.
  7. See Measuring Response Time for details on definition of latency and jitter.